The 3D-IC approach uses a combination of standard single damascene techniques, wafer thinning, and direct Cu—Cu thermo-compression bonding. Hybrid bonding is a cost-effective, die-to-wafer integration processes for vertical stacking and high density die-to-die interconnecting.
In general, direct hybrid bonding is compatible with both die-to-die (D2D) and wafer-on-wafer (WoW) bonding. In direct hybrid bonding, a dual damascene copper and silicon oxide hybrid interface between dies serves as both the full-area substrate bonding mechanism and the electrical connection between pads and/or vias on respective dies.
Design-for-Testing or Design for Testability (“DFT”) refers to integrated circuit design techniques that add certain testability features to a hardware product design. The DFT features make it easier to develop and apply various manufacturing tests for the designed hardware. The purpose of manufacturing tests is to validate that the hardware products contain no manufacturing defects that could adversely affect the product's proper functioning. Scan chain is one example of a technique implemented in a DFT process.